Implementing FFT-based Digital Channelized Receivers on FPGA Platforms [Elektronisk resurs]
-
Sanchez, Miguel A. (författare)
-
Garrido, Mario 1981- (författare)
-
Lopez-Vallejo, Marisa (författare)
-
Grajal, Jesus (författare)
- Institute of Electrical and Electronics Engineers (IEEE) 2008
- Engelska.
-
Ingår i: IEEE Transactions on Aerospace and Electronic Systems. - 0018-9251. ; 44:4, 1567-1585
-
Läs hela texten
-
Läs hela texten
-
Läs hela texten
Sammanfattning
Ämnesord
Stäng
- This paper presents an in-depth study of the implementationand characterization of fast Fourier transform (FFT) pipelinedarchitectures suitable for broadband digital channelized receivers.When implementing the FFT algorithm on field-programmablegate array (FPGA) platforms, the primary goal is to maximizethroughput and minimize area. Feedback and feedforwardarchitectures have been analyzed regarding key designparameters: radix, bitwidth, number of points and stage scaling.Moreover, a simplification of the FFT algorithm, the monobitFFT, has been implemented in order to achieve faster real timeperformance in broadband digital receivers. The influence ofthe hardware implementation on the performance of digitalchannelized receivers has been analyzed in depth, revealinginteresting implementation trade-offs which should be taken intoaccount when designing this kind of signal processing systems onFPGA platforms.
Ämnesord
- Engineering and Technology (hsv)
- Electrical Engineering, Electronic Engineering, Information Engineering (hsv)
- Other Electrical Engineering, Electronic Engineering, Information Engineering (hsv)
- Teknik och teknologier (hsv)
- Elektroteknik och elektronik (hsv)
- Annan elektroteknik och elektronik (hsv)
- TECHNOLOGY (svep)
- Electrical engineering, electronics and photonics (svep)
- Electrical engineering (svep)
- TEKNIKVETENSKAP (svep)
- Elektroteknik, elektronik och fotonik (svep)
- Elektroteknik (svep)
Indexterm och SAB-rubrik
- Fast Fourier Transform (FFT)
- Pipelined Architecture
- Very-large-scale integration (VLSI)
- Channelized Receiver
- FPGA
Inställningar
Hjälp
Beståndsinformation saknas