A Study of Design Efficiency with a High-Level Language for FPGAs [Elektronisk resurs]

• Over the years reconfigurable computing devices such as FPGAs have evolved from gate-level glue logic to complex reprogrammable processing architectures. However, the tools used for mapping computations to such architectures still require the knowledge about architectural details of the target device to extract efficiency. A study of the Mobius language and tools is presented in this paper, with a focus on generated hardware performance. A number of streaming and memory-intensive applications have been developed and the results have been compared with the corresponding implementations in VHDL and a behavioral hardware description language. Based upon experimental evidences, it is concluded that Mobius, a minimal parallel processing language targeted for reconfigurable architectures, enhances productivity in terms of design time and code maintainability without considerably compromising performance and resources. 

Ämnesord

Engineering and Technology  (hsv)

Teknik och teknologier  (hsv)

Natural Sciences  (hsv)

Computer and Information Science  (hsv)

Computer Science  (hsv)

Naturvetenskap  (hsv)

Data- och informationsvetenskap  (hsv)

Datavetenskap (datalogi)  (hsv)

TECHNOLOGY  (svep)

TEKNIKVETENSKAP  (svep)

TECHNOLOGY  (svep)

Information technology  (svep)

Computer science  (svep)

TEKNIKVETENSKAP  (svep)

Informationsteknik  (svep)

Datavetenskap  (svep)

Computer and Systems Science  (oru)

Data- och systemvetenskap  (oru)

Indexterm och SAB-rubrik

FPGA

Mobius language

VHDL

behavioral hardware description language

high-level language

minimal parallel processing language

reconfigurable computing device

eprogrammable processing architecture